Your Open-Source path to multi-million gate Verilog+VHDL designs

07.08.06 -- 2006.07 Released! Improved Verilog Support, RTL Analyzer Tool and more!

Letter to users regarding 2006.07 release

12.11.01 -- EE Times Article by Richard Goering on ChipVault www.eetimes.com and in www.eedesign.com
and a local copy when the magazine links eventually die OEG20011211S0034.html

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GPL License

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ChipVault is a VHDL and Verilog Chip Design Organization tool which improves design efficiency by:

Providing the ability to Navigate and Edit files Hierarchically.
Automatically generating Schematic Component Port views of VHDL and Verilog RTL files.
Automating RTL instantiation and template generation.
Providing Revision Control (designed for HW, not SW development).
Supporting External Tool Hooks (bottom-up vcoms,etc).
Providing an Issue Tracking Log with sorting.
Providing Netlist sorting and hierarchy viewing.
Supporting web-sharing of RTL files (both encrypted and clear).

Fast and Nimble. ChipVault was designed by an ASIC designer who designs million gate ASICs using Vi. ChipVault launches as fast as Vi and is platform portable from UNIX->Linux->Win32.

Comments or questions regarding Chip Vault, please email khubbard@users.sourceforge.net.

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