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January 16, 2002


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  • ASIC designer creates design management tool

    By Richard Goering
    EE Times
    (12/13/01 09:59 a.m. EST)

    ISSAQUAH, Wash. — An open-source "design organization" tool created by Kevin Hubbard, an ASIC designer at Siemens Ultrasound, promises to help manage large chip design projects without the overhead of commercial, graphically oriented tools. Called ChipVault, the offering provides Verilog or VHDL hierarchical file organization, revision control, issue tracking, hierarchy viewing, block instantiation and hooks for launching EDA tools.

    Although Siemens Ultrasound uses ChipVault, Hubbard developed the tool on his own. The first "usable" version became available last month under the GNU Public License (GPL) at chipvault.sourceforge.net.

    "I saw a need for a lightweight tool capable of handling really large designs," Hubbard said. While ChipVault can handle projects with hundreds of files, it's written in Perl and is fast, small and efficient, he claimed. In fact, said Hubbard, ChipVault takes no more time to launch than the popular Vi editor.

    "Using Vi is the fastest way to implement large designs, but if a million-gate design has 10,000-gate blocks, that's going to be 100 design files," said Hubbard. "That's too much to manage by hand. The idea here is to have a tool that wraps around Vi or Emacs and handles the hierarchy for you."

    Feature focus

    ChipVault also provides some revision control capabilities, but without all the features offered by software-oriented tools like the Unix RCS utility or Clearcase, Hubbard said. Instead, it focuses on features truly needed by hardware engineers, such as a facility that prevents one RTL file from being checked out by multiple engineers.

    ChipVault automatically sorts and displays design files hierarchically, and lets designers navigate through that hierarchy. It also provides a netlist hierarchy viewing feature that can filter out insignificant flip-flops and gates to display only large modules. That feature keeps tabs on components that have been inferred by synthesis.

    "I like to be intimate with my gate inferences, and I don't always trust Synopsys to do the optimal job," said Hubbard. "I've used this [hierarchy viewing] feature a lot in my current design to sanity-check Synopsys RTL gate inferences against what I expected DC [Synopsys' Design Compiler] to do."

    A built-in ChipVault tool provides a VHDL utility for reading entity declarations and deciphering port declarations. ChipVault uses the information to draw a block diagram of all signals going in and out of a block.

    ChipVault will generate a database for tracking issues that come up during design. The program also has the ability to define associations among files and provide access to up to 100 related reports for quick viewing.

    The tool is "very customizable," Hubbard said. "It's designed for hardware engineers familiar with Perl. All the configuration is done in Perl, and you can launch any kind of Unix or Perl tool from within ChipVault. There's a toolbar you can configure to launch anything you want."

    Graphical interface wanted

    At present, ChipVault has a text interface only. Hubbard said that he is attempting to get a wxPerl port up and running so that he can build a graphical user interface. Hubbard also is aiming to add a feature that will display port views for "child" blocks along with the current block.

    As with all open-source products, support is minimal.

    "I want to hear from users if they have technical problems," Hubbard said. "If ChipVault is unable to read netlists or RTL code, I'll want to see design examples.

    "And I'll add features if it makes sense, but I'm not accepting money for it."



     


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