***************************************************************** iv) Tutorial Text: ChipVault Tutorial 11-12-2002 This Tutorial is a quick 10 minute walk-thru of the major features in ChipVault. You will need to de-tar the example files from http:\\chipvault.sourceforge.net\tutorial.tar.gz %gunzip tutorial.tar.gz %tar -xvf tutorial.tar Index: Step-1) File Setup Step-2) Reading in an existing Design and generating a hlist.txt file Step-3) Navigating the ChipVault Hierarchy Interface Step-4) Port Viewing Step-5) File Editting Step-6) Tool Bar Step-7) Revision Control. CheckIn/CheckOut Step-8) Issue List Step-9) VHDL Module Generation Step-10) Bottom Up Compiles Step-11) Schematic Block Printing Step-12) RTL Viewer Step-13) Admin Control of Checkins Step-14) Netlist Viewing Step-1) File Setup o) Copy cv.pl into the tutorial/src directory o) %cd tutorial/src Step-2) Reading in an existing Design and generating a hlist.txt file o) %perl cv.pl top.vhd This will read in the top.vhd file and find all the children by scanning thru the *.vhd and *.v files in the same subdirectory. o) Press when prompted for the Filter Value. If the VHDL and Verilog files were read in OK, you should now see a hierarchy tree of the example design. o) Quit ChipVault by pressing . Look at the hlist.txt file that CV built and then restart ChipVault in the normal fast mode: o) %perl cv.pl (or just %cv.pl if perl is in path and chmod +x) Step-3) Navigating the ChipVault Hierarchy Interface o) Use the cursors keys (or to go up and down the hierachy. Note the "file=" box will display the actual file name you are on. o) Navigate to "german" and press bar. This should collapse the "german" module and all of its children modules should now be invisible. Press bar again, and the child modules should re-appear. o) Press <3>. This will collapse everything below 3 levels deep. o) Press (4). This will collapse everything below 4 levels deep. Step-4) Port Viewing o) Navigate to module "top" and press the

key. This will display all the port I/O to this module. Press . Step-5) File Editting o) Navigate to module "metrics" and press key. This should launch VI and open metrics.vhd. o) Type <:> to exit VI and go back to ChipVault. Step-6) Tool Bar o) Press to bring the Tool Bar up. o) Scroll thru the Tool Bar window using up and down cursor keys ( or and ) until "Edit (Emacs)" under "Editors" appears and press . This should bring up "metrics.vhd" in a Emacs Edit window. The key is now assigned to "Edit (Emacs)" as indicated by the top line of the ChipVault screen. o) Quit Emacs and Cursor down to "modelo" and press and another instance of Emaces will be launched, but with modelo.vhd. o) Quit Emacs and Cursor down to "german" and ool to Edit (fork) This will launch Vi and send the process in the background, keeping ChipVault active. o) Press to bring up Bang History. Press <2> to select the Emacs. o) Press <@> to bring up Macro Tool. Press <1> to select Edit. Step-7) Revision Control. CheckIn/CheckOut a) Check Out a File o) Cursor back to "metrics", hit for tool and select "check_out" . ( or just press key over metrics ) You should have just checked out the file metrics.vhd . If this worked, to the right of "metrics" you should see your user name in the "CheckedOut" column. o) Cursor over to your user name and you should see "wip.metrics.vhd" at the bottom-left of the screen instead of original "metrics.vhd". This Work-In-Progress (wip) file is a copy of metrics.vhd for you to work on. o) Press to make changes to wip.metrics.vhd using your default editor. b) Diff your Checked Out file o) Cursor back to the left column over "metrics" and press and select "Diff CO'd file". You should get an error message from Diff. Cursor down to "log.txt" and select "Edit" from the tool bar to view the diff output. c) Check In a File o) Cursor back up to your username under the CheckedOut column to the right of "metrics". Tool Bar select "check_in". ( or just press key over username ) o) When prompted, type a short sentence about the change you made. ChipVault will now copy "wip.metrics.vhd" to "metrics.vhd" In the process it will destroy the original "metrics.vhd" and create a tar archive of the new "metrics.vhd" you modified. d) View Change Log o) Cursor to "metrics" then cursor right twice. The top-left should show [ 2 HistoryLog ] and your cursor should be on history_log.metrics.vhd.txt. o) Select "Edit" from your tool bar and view the history change file. e) View Archive Log o) Cursor right again The top-left should show [ 3 TAR-Ball Archive List ] View the archive_list.metrics.vhd.txt file to see what archives have been auto-generated by ChipVault. Step-8) Issue List o) Select Issue_List_View from the Tool Bar. Press <1> to sort the issues by issue number. Press <2> to sort the issues by Reporter. Press <3> to sort the issues by AssignTo. Press <4> to sort the issues by Module name. Scroll to a desired issue and press to view the full description. o) Select tool bar from the main screen and walk thru the issue generation process. Step-9) VHDL/Verilog Module Generation o) Cursor over to "grolsch" and tool-bar select "generate_VHDL" o) Type in "austrian" o) Type when prompted for instantiating "grolsch.vhd" o) Type "foo" 16 in for adding new foo(15:0). o) Type "bar" for new net bar(15:0). o) Type "bob" 1 out for new net bob. o) Type to exit this loop. o) Cursor to the bottom of the ChipVault screen and edit "austrian" module at the very bottom. This should be a new VHDL module with the nets you described and it should instantiate "grolsch.vhd". o) You've added a new module, now you need to place it in the design hierarchy. You could edit "beers", add "austrian" insantiations, delete the original hlist.txt file and start-over from step-1 OR o) cursor up to top of the screen to hlist.txt and edit. Type a new line above "german" with "austrian" and "austrian.vhd" The cursor position of the 1st "a" of austrian MUST be at the same spot as the "g" of "german". This is how ChipVault knows the design hierarchy. Yank and Pase the grolsch line from under "german" and place it under "austrian". o) Quit ChipVault () and restart chip vault with no params. %perl cv.pl You should see your new module in the correct place in hiearchy Note: Module Generation allows you to instantiate Verilog from VHDL and vice-versa. Step-10) Bottom Up Compiles o) Get ModelSim stuff setup properly (see example). o) Cursor to "german" and press to collapse. o) ToolBar select "Compile". This will vcom german.vhd. Any errors will dump to log.txt o) Cursor to "german" and press to expand. o) ToolBar select "Compile". This will vcom cap.v, light.vhd, dark.vhd, amstel, heini, becks and then finally german. Step-11) Schematic Block Printing o) Place the cursor on the top of the architecture you want a printout of. Select block_print from the ToolBar EDA Tools list. o) The current directory will now contain print.txt and print.pdf suitable for printing. Note: Adobe-Acrobat likes to cache pdf files so you often need to quit and restart Acrobat if you re-gen print.pdf. Step-12) RTL Viewer o) Place cursor on component "top" and select tool cv_rtl_viewer. o) Cursor up,down left and right thru the top.vhd file. o) Page-Up and Page-Down using Ctrl-U and Ctrl-D. o) Position cursor on the line: "v component metrics" o) Press to expand the component declaration for metrics. o) Repeat the same for foo_proc, u_metrics, etc. Step-13) Admin Control of Checkins o) Place cursor on the top of the hierarchy you want to make ReadOnly. Toggle expand/collapse so that all files are visible which you wish to chmod. Scroll to admin tools on the tool bar and select ReadOnly. o) To allow a user to checkin a file, place cursor on the mainbranch version of that file, collapse the view so that his children are not visible. Scroll to admin tools on the tool bar and select ReadWrite. The user may now checkin his file over the mainline file. After the checkin, you'll want to set the permission back to ReadOnly. Step-14) Netlist Viewing o) Start ChipVault as before but in a directory with only your netlist. /tutorial/netlist/% cv.pl top.vhd o) Select a decent filter value of say 10 or 20 so that you won't have a hierarchy view full of ANDs and Flops. o) You should now have a hierarchy view of all the large netlist blocks. TheEnd. See the on-line Help FAQ for more info. (end)